// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  dvpp_reg_offset_field.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  Huawei
// Version       :  1.0
// Date          :  2017/11/13
// Description   :  The description of Ascend 310 project
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/05/16 10:46:15 Create file
// ******************************************************************************

#ifndef __DVPP_REG_OFFSET_FIELD_H__
#define __DVPP_REG_OFFSET_FIELD_H__

#define DVPP_VENC_LEN    40
#define DVPP_VENC_OFFSET 0

#define DVPP_VPC3_REG1_LEN    40
#define DVPP_VPC3_REG1_OFFSET 0

#define DVPP_VPC3_REG0_LEN    40
#define DVPP_VPC3_REG0_OFFSET 0

#define DVPP_VPC2_REG1_LEN    40
#define DVPP_VPC2_REG1_OFFSET 0

#define DVPP_VPC2_REG0_LEN    40
#define DVPP_VPC2_REG0_OFFSET 0

#define DVPP_VPC1_REG1_LEN    40
#define DVPP_VPC1_REG1_OFFSET 0

#define DVPP_VPC1_REG0_LEN    40
#define DVPP_VPC1_REG0_OFFSET 0

#define DVPP_VPC0_REG1_LEN    40
#define DVPP_VPC0_REG1_OFFSET 0

#define DVPP_VPC0_REG0_LEN    40
#define DVPP_VPC0_REG0_OFFSET 0

#define DVPP_VDEC1 REG_LEN    40
#define DVPP_VDEC1 REG_OFFSET 0

#define DVPP_VDEC0 REG_LEN    40
#define DVPP_VDEC0 REG_OFFSET 0

#define DVPP_JPEG_REG1_LEN    40
#define DVPP_JPEG_REG1_OFFSET 0

#define DVPP_JPEG_REG0_LEN    40
#define DVPP_JPEG_REG0_OFFSET 0

#define DVPP_PNGD5_REG_LEN    40
#define DVPP_PNGD5_REG_OFFSET 0

#define DVPP_PNGD4_REG_LEN    40
#define DVPP_PNGD4_REG_OFFSET 0

#define DVPP_PNGD3_REG_LEN    40
#define DVPP_PNGD3_REG_OFFSET 0

#define DVPP_PNGD2_REG_LEN    40
#define DVPP_PNGD2_REG_OFFSET 0

#define DVPP_PNGD1_REG_LEN    40
#define DVPP_PNGD1_REG_OFFSET 0

#define DVPP_PNGD0_REG_LEN    40
#define DVPP_PNGD0_REG_OFFSET 0

#define DVPP_I2C2_REG_LEN    40
#define DVPP_I2C2_REG_OFFSET 0

#define DVPP_I2C1_REG_LEN    40
#define DVPP_I2C1_REG_OFFSET 0

#define DVPP_SPI2_REG_LEN    40
#define DVPP_SPI2_REG_OFFSET 0

#define DVPP_SPI1_REG_LEN    40
#define DVPP_SPI1_REG_OFFSET 0

#define DVPP_SPI0_REG_LEN    40
#define DVPP_SPI0_REG_OFFSET 0

#define DVPP_GPIO3_REG_LEN    40
#define DVPP_GPIO3_REG_OFFSET 0

#define DVPP_GPIO2_REG_LEN    40
#define DVPP_GPIO2_REG_OFFSET 0

#define DVPP_UART1_REG_LEN    40
#define DVPP_UART1_REG_OFFSET 0

#define DVPP_MDIO_REG_LEN    40
#define DVPP_MDIO_REG_OFFSET 0

#define DVPP_IOMUX_REG_LEN    40
#define DVPP_IOMUX_REG_OFFSET 0

#define DVPP_EXMBIST0_REG_LEN    40
#define DVPP_EXMBIST0_REG_OFFSET 0

#define DVPP_DDRC3_REG1_LEN    40
#define DVPP_DDRC3_REG1_OFFSET 0

#define DVPP_DDRC3_REG0_LEN    40
#define DVPP_DDRC3_REG0_OFFSET 0

#define DVPP_DDRC2_REG1_LEN    40
#define DVPP_DDRC2_REG1_OFFSET 0

#define DVPP_DDRC2_REG0_LEN    40
#define DVPP_DDRC2_REG0_OFFSET 0

#define DVPP_DDRC1_REG1_LEN    40
#define DVPP_DDRC1_REG1_OFFSET 0

#define DVPP_DDRC1_REG0_LEN    40
#define DVPP_DDRC1_REG0_OFFSET 0

#define DVPP_DDRC0_REG1_LEN    40
#define DVPP_DDRC0_REG1_OFFSET 0

#define DVPP_DDRC0_REG0_LEN    40
#define DVPP_DDRC0_REG0_OFFSET 0

#define DVPP_SCHE1_REG_LEN    40
#define DVPP_SCHE1_REG_OFFSET 0

#define DVPP_SMMU1_REG3_LEN    40
#define DVPP_SMMU1_REG3_OFFSET 0

#define DVPP_SMMU1_REG2_LEN    40
#define DVPP_SMMU1_REG2_OFFSET 0

#define DVPP_SMMU1_REG1_LEN    40
#define DVPP_SMMU1_REG1_OFFSET 0

#define DVPP_SMMU1_REG0_LEN    40
#define DVPP_SMMU1_REG0_OFFSET 0

#define DVPP_SUBCTRL0_REG_LEN    40
#define DVPP_SUBCTRL0_REG_OFFSET 0

#define DVPP_DISP_REG_LEN    40
#define DVPP_DISP_REG_OFFSET 0

#define DVPP_SCHE0_REG_LEN    40
#define DVPP_SCHE0_REG_OFFSET 0

#define DVPP_FTE_REG_LEN    40
#define DVPP_FTE_REG_OFFSET 0

#define DVPP_SMMU0_REG3_LEN    40
#define DVPP_SMMU0_REG3_OFFSET 0

#define DVPP_SMMU0_REG2_LEN    40
#define DVPP_SMMU0_REG2_OFFSET 0

#define DVPP_SMMU0_REG1_LEN    40
#define DVPP_SMMU0_REG1_OFFSET 0

#define DVPP_SMMU0_REG0_LEN    40
#define DVPP_SMMU0_REG0_OFFSET 0

#endif // __DVPP_REG_OFFSET_FIELD_H__
